library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity instruction_decode is
generic (numBit 	: integer := 32;
			opSize	: integer := 6;
			regSize	: integer := 5);
port(	clk			: in  std_logic;
		rst			: in  std_logic;
		enb			: in  std_logic;
		Rs 			: in  std_logic_vector (regSize-1 downto 0);
		Rt 			: in  std_logic_vector (regSize-1 downto 0);
		Rd 			: in  std_logic_vector (regSize-1 downto 0);
		Imm_in		: in  std_logic_vector (numBit/2-1 downto 0);
		mem_in		: in  std_logic_vector (numBit-1 downto 0); 	-- data from the WB stage
		w_en			: in  std_logic;							 	 		-- write enable from CU
		A_out			: out std_logic_vector (numBit-1 downto 0);
		B_out			: out std_logic_vector (numBit-1 downto 0);
		Imm_out		: out std_logic_vector (numBit-1 downto 0)
);
end instruction_decode;

architecture Structural of instruction_decode is
component reg is
generic (N : integer := 32);
port( clock		: in  std_logic;
		reset		: in  std_logic;
		enable	: in  std_logic;
		data_in 	: in  std_logic_vector (N-1 downto 0);
		data_out : out std_logic_vector (N-1 downto 0)
);
end component;

component sign_ext is
generic (N : integer := 32);
port(	input : in std_logic_vector (N/2-1 downto 0);
		output: out std_logic_vector (N-1 downto 0)
);
end component;

component Register_File is
generic (N 		 : positive := 32;		--number of bits in the registers
         N_ADDR : positive := 5);		--address size (determines number of registers)
port( clock 	  : in  std_logic;
		reset 	  : in  std_logic;
		port_S_addr: in  std_logic_vector (N_ADDR-1 downto 0);
		port_T_addr: in  std_logic_vector (N_ADDR-1 downto 0);
		port_D_addr: in  std_logic_vector (N_ADDR-1 downto 0);
		write_D_EN : in  std_logic;
		port_D_IN  : in  std_logic_vector (N-1 downto 0);  --content to be written (Data In)
		port_S_OUT : out std_logic_vector (N-1 downto 0);  --content to be read
		port_T_OUT : out std_logic_vector (N-1 downto 0)   --content to be read
);
end component;

signal sign_out : std_logic_vector (numBit-1 downto 0);
signal memA_out : std_logic_vector (numBit-1 downto 0);
signal memB_out : std_logic_vector (numBit-1 downto 0);

--signal Rs : std_logic_vector (regSize-1 downto 0);
--signal Rt : std_logic_vector (regSize-1 downto 0);
--signal Rd : std_logic_vector (regSize-1 downto 0);
begin

--Rs <= r_s;
--Rt <= r_t;
--Rd <= r_d;

REG_FILE: Register_File generic map (numBit,regSize) port
map (clk,rst,Rs,Rt,Rd,w_en,mem_in,memA_out,memB_out);

SIGN: sign_ext generic map (numBit) port
map (Imm_in, sign_out);

A: reg generic map (numBit) port 
map (clk, rst, enb, memA_out, A_out);

B: reg generic map (numBit) port 
map (clk, rst, enb, memB_out, B_out);

Imm: reg generic map (numBit) port 
map (clk, rst, enb, sign_out, Imm_out);

end Structural;
